1. Field of the Invention
The present invention relates to a process for forming an integrated circuit comprising non-volatile memory cells and peripheral transistors.
Specifically, the present invention relates to a process providing for the implementation in a monocrystalline silicon substrate of at least one matrix of memory cells. In each memory cell, a floating gate and a control gate, both electroconductive, are mutually electrically insulated by means of an intermediate dielectric multilayer. There is also provided simultaneous formation, peripheral to the matrix zones, of at least one first type of MOS transistor.
The present invention also relates to an integrated circuit of the above mentioned type comprising non-volatile memory cells having an intermediate dielectric multilayer and at least one type of peripheral transistors.
2. Discussion of the Related Art
As is known in the field of electronic semiconductor technology, in order to reduce the area of integrated circuits there is a tendency towards ever greater integration scales with a reduction of component sizes. This has led to improvement of the quality of the materials used and to optimization of the processes for their formation.
The present invention relates to the field of the development of the techniques of formation of dielectric materials in a single integrated circuit, and in the formation of layers of different thickness and composition which perform different functions. On one hand the dielectric materials act as insulators providing electrical insulation of conductive layers and creating a barrier against contaminating substances coming from the outside ambient, while on the other hand the dielectric materials as active dielectrics allowing the passage of charges between layers of conductive materials.
In order to improve the quality and functionality of the above mentioned dielectrics it has been proposed in relatively recent times to provide multiple superimposed layers, in particular using layers of silicon oxides and/or silicon nitrides.
In the specific field of application of the present invention there are provided integrated memory circuits including, in addition to a plurality of memory cells arranged in one or more matrixes, external or peripheral circuits in which components are structurally similar to the cells and are provided by the same technology. Specific reference is made to MOS transistors.
Non-volatile memories, to which specific reference is made in the present invention, comprise different classes of devices or products which differ from each other by the structure of the individual memory cell and the type of application. Specifically reference is made to read-only memories which can be electrically programmed and erased (Erasable Programmable Read Only Memories) and specifically EPROM, EEPROM or FLASH. These types of memories can be distinguished from one another as some of them are both erasable and electrically programmable, while others require, e.g., ultraviolet light to be erased. For data storage, memory cells comprise in all cases a floating-gate MOS transistor integrated on a substrate usually of monocrystalline silicon. The amount of charge contained in the floating gate determines the logical state of the cell. Non-volatile memory cells are programmed in a discrete number of logical states allowing memorization of one or more bits per cell. In standard cells, for exarnple, programming is provided in two logical states, written and erased, with memorization of one bit per cell.
The floating gate of electroconductive material, normally polysilicon, i.e., polycrystalline silicon or `poly`, is completely surrounded by insulating material. In particular, over the floating gate a dielectric layer, so-called intermediate dielectric or interpoly, insulates the floating gate from an overlying control gate also of electroconductive material. The control gate can consist alternatively of a single polysilicon layer or of a double polysilicon trasversal silicide layer and is coupled electrically to a programming terminal.
As known to those skilled in the art the interpoly dielectric is particularly critical in terms of charge retention. This dielectric can consist of a silicon oxide layer in accordance with well known techniques. Development of the technology has also revealed as advantageous the use of a multilayer intermediate dielectric. This preserves the insulating characteristics of the intermediate layer while avoiding the problem of loss of charge from the floating gate to the control gate, whether over the long term or when a high programming potential is applied to the control gate. In particular, as known to those skilled in the art, this class of intermediate dielectrics comprises a triple layer of silicon oxide, silicon nitride and silicon oxide, the so-called ONO. As described e.g. in U.S. Pat. No. 5,104,819, after formation of an underlying silicon oxide layer and deposition of silicon nitride, an upper silicon oxide layer is formed by deposition instead of by the conventional oxidation of the underlying nitride. This type of dielectric achieved has good charge retention capability and increased capacitive coupling between floating gate and control gate.
Regarding the so-called external or peripheral transistors, they are incorporated in circuits outside the memory cell matrix, e.g., logical, or matrix control circuits. Specifically in the framework of the present invention, reference is made, as indicated above, to MOS transistors.
MOS transistors include an active dielectric, the so-called gate dielectric, placed between the substrate and a gate of electroconductive material, normally polysilicon. Usually the active dielectric consists of a silicon oxide layer formed at a high temperature by oxidation of the substrate.
To minimize the number of production process steps of the entire integrated circuit it is known to make the memory cells and peripheral transistors simultaneously, as mentioned above. Specifically, the present invention falls within a class of processes in which the polysilicon layer making up the gate of the peripheral transistors corresponds to the formation process step in which the control gate polysilicon layer of the memory cells is formed. In these processes the intermediate dielectric of the memory cells and the gate dielectric of the transistors of the circuitry are also formed simultaneously.
A process of the prior art comprises essentially the following steps:
formation of a first polysilicon layer of the floating gate and of the intermediate dielectric after formation of a gate silicon oxide layer of the cells, PA1 removal of the above mentioned layers from the zones in which the transistors of the circuitry are formed; PA1 formation, by means of high-temperature substrate oxidation, of a silicon oxide layer in the areas in which the peripheral transistors are to be formed; and PA1 formation of a second polysilicon layer of the control gate of the cells and which also constitutes the gate of the peripheral transistors. PA1 removal of the silicon oxide layer from the areas of the additional transistor type; and PA1 formation, again by substrate oxidation, of another silicon oxide layer in the areas of both transistor types. PA1 removal from the matrix peripheral zones of the above mentioned layers; PA1 deposition of said upper silicon oxide layer over the memory cells and over the substrate in the area in which the peripheral transistors are formed; and PA1 formation of a first silicon oxide layer at least in the peripheral transistor areas.
If it is necessary to form two peripheral transistor types with different gate oxide thicknesses, before formation of the second polysilicon layer, the prior art process comprises the additional steps of:
Recently, in the framework of the research for new types of dielectrics using MOS transistors, there was proposed use of a gate dielectric comprising, in addition to a silicon oxide layer achieved by high-temperature thermal oxidation, an overlying layer also of silicon oxide but achieved by deposition. The benefits of such a composite dielectric are described for example in an article entitled "Thin CVD stacked gate dielectric for ULSI technology" by Hsing-Huang Tseng et al, IEDM Technical Digest, pages 321-324, 1993.
In U.S. Pat. No. 5,104,819 mentioned above there is disclosed formation of a memory cell matrix having ONO type interpoly dielectric and peripheral transistors with gate dielectric including another deposited silicon oxide layer. The deposited silicon oxide layer of the intermediate dielectric multilayer of the cells also constitutes the gate dielectric upper layer of the peripheral transistors and is formed successively over a first gate thermal silicon oxide layer.
This manufacturing process however only permits formation of a single type of peripheral transistor. In addition the silicon oxide deposited to complete the gate dielectric is not good quality if its deposition is not followed by a so-called thermodynamic annealing process, as indicated to be necessary in the above mentioned article.
An object of the present invention is to conceive a process for the formation of non-volatile memory cells and peripheral transistors permitting achievement of a gate dielectric and an intermediate dielectric of good quality, in order to achieve an integrated circuit having characteristics of great reliability and functionality.
Another object is to provide this circuit while minimizing the number of process steps and thus the production costs.
Another object is to provide a process which is particularly flexible and usable, for example, in the simultaneous formation of peripheral transistors having different gate dielectrics.
Another object of the present invention is to provide a process usable either with intermediate dielectrics comprising only silicon oxide or consisting of the triple ONO layer.